One embodiment of the invention relates to a method for forming trench memory cell structures each having a trench capacitor and a selection transistor for selectively addressing the trench capacitor.
Memory cells of dynamic random access memories (DRAMs) include a storage capacitor for storing an electrical charge characterizing an information content of the memory cell, and also a selection transistor for addressing the storage capacitor.
In trench memory cells, the storage capacitors are formed as trench capacitors along hole trenches which are introduced into a semiconductor substrate from a substrate surface. The selection transistors are provided as field effect transistors each having an active zone formed in the semiconductor substrate and a gate electrode bearing on the semiconductor substrate.
The active zone comprises two source/drain zones which are spaced apart from one another by a channel zone and are in each case formed as doped sections of the semiconductor substrate.
A first source/drain zone in a node section of the active zone is connected to a storage electrode of the trench capacitor that is provided in the interior of the hole trench. A second source/drain zone in a bit contact section of the active zone is connected to a bit contact structure via which the trench memory cell is connected to a data line.
In a manner dependent on a potential at the gate electrode, when the memory cell is addressed, a conductive channel is produced between the two source/drain zones of the selection transistor and the storage electrode is connected to the data line. In the non-addressed state of the memory cell, the storage electrode is insulated from the data line.
The storage electrode adjoins the first source/drain zone in an electrically conductive manner in the semiconductor substrate in the region of a contact window (buried strap window).
The alignment of the source/drain zones with respect to the gate electrodes is essential to the functionality of the selection transistor.
A method of aligning the source/drain zones or sections of the source/drain zones precisely with respect to the gate electrodes is described in DE 102 40 429 A1 (Popp et al.).
Accordingly, gate electrode stacks (also called gate stacks hereinafter) with a base layer made of polysilicon are formed above a semiconductor substrate with trench capacitors on a gate dielectric. An implantation for forming at least one section of the doped source/drain zones is effected in a self-aligned manner with respect to the edges of the gate stacks. The implantation of the doping is performed before or after the conclusion of a sidewall oxidation of the polysilicon layer. The formation of the sidewall oxide is combined with the implantation and the extent of the doped zones below the gate stacks is thereby controlled by means of the sidewall oxidation.
In order to form a reliable, low-resistance connection between the storage electrode of the trench capacitor and the first source/drain zone of the selection transistor, an implantation is necessary whose outdiffusion under the adjacent gate stacks is to be kept low, so that the sidewall oxide is not sufficient for spacing apart the reinforcement implant with respect to the gate stacks.